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| DDU8C3 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE (SERIES DDU8C3) FEATURES * * * * * * Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 2 10 T L fan-out capability IN T2 T4 GND data 3 (R) delay devices, inc. PACKAGES 1 2 3 4 8 7 6 5 VDD T1 T3 T5 DDU8C3-xx DIP DDU8C3-xxA1 Gull-Wing FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The DDU8C3-series device is a 5-tap digitally buffered delay line. The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an T1-T5 Tap Outputs amount determined by the device dash number (See Table). For dash VDD +3.3 Volts numbers 5020 and above, the total delay of the line is measured from IN to GND Ground T5, and the nominal tap-to-tap delay increment is given by one-fifth of the total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay increment is given by one-fourth of the total delay. SERIES SPECIFICATIONS * * * * * * Minimum input pulse width: 40% of total delay Output rise time: 2ns typical Supply voltage: 3.3VDC 0.3V Supply current: ICCL = 40a typical ICCH = 7ma typical Operating temperature: -40 to 85 C Temp. coefficient of total delay: 300 PPM/C DASH NUMBER SPECIFICATIONS Part Number DDU8C3-5004 DDU8C3-5006 DDU8C3-5008 DDU8C3-5010 DDU8C3-5012 DDU8C3-5014 DDU8C3-5020 DDU8C3-5025 DDU8C3-5030 DDU8C3-5035 DDU8C3-5040 DDU8C3-5045 DDU8C3-5050 DDU8C3-5060 DDU8C3-5075 DDU8C3-5100 DDU8C3-5125 DDU8C3-5150 DDU8C3-5175 DDU8C3-5200 DDU8C3-5250 Total Delay (ns) 4 1.0 * 6 1.0 * 8 2.0 * 10 2.0 * 12 2.0 * 14 2.0 * 20 2.0 25 2.0 30 2.0 35 2.0 40 2.0 45 2.25 50 2.5 60 3.0 75 3.75 100 5.0 125 6.5 150 7.5 175 8.0 200 10.0 250 12.5 Delay Per Tap (ns) 1.0 0.5 1.5 0.5 2.0 1.0 2.5 1.0 3.0 1.0 3.5 1.0 4.0 1.0 5.0 1.5 6.0 1.5 7.0 1.8 8.0 2.0 9.0 2.0 10.0 2.0 12.0 2.0 15.0 2.5 20.0 3.0 25.0 3.0 30.0 3.0 35.0 4.0 40.0 4.0 50.0 5.0 3.0ns 25% 25% 25% 25% VDD IN T1 T2 T3 T4 T5 GND Functional diagram for dash numbers < 5020 20% 20% 20% 20% 20% VDD IN T1 T2 T3 T4 T5 GND Functional diagram for dash numbers >= 5020 * Total delay is referenced to first tap output Input to first tap = 3.0ns 1ns NOTE: Any dash number between 5004 and 5250 not shown is also available. (c) 2000 Data Delay Devices Doc #00115 5/19/00 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 DDU8C3 APPLICATION NOTES HIGH FREQUENCY RESPONSE The DDU8C3 tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. POWER SUPPLY BYPASSING The DDU8C3 relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.00V to 3.60V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current SYMBOL VOH VOL IOH IOL VIH VIL IIH MIN 3.00 TYP 3.20 0.10 MAX UNITS V V mA mA V V A NOTES VDD = 3.3, IOH = MAX VIH = MIN, VIL = MAX VDD = 3.3, IOL = MAX VIH = MIN, VIL = MAX 0.30 -24.0 24.0 2.50 0.80 0.10 VDD = 3.3 Doc #00115 5/19/00 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com 2 DDU8C3 PACKAGE DIMENSIONS 8 7 6 5 Lead Material: Nickel-Iron alloy 42 TIN PLATE 1 2 3 4 .500 MAX. .280 MAX. .290 MAX. .015 TYP. .010.002 .018 TYP. .070 MAX. .300.010 3 Equal spaces each .100.010 Non-Accumulative .350 MAX. DDU8C3-xx (DIP) .020 TYP. 8 7 6 5 .040 TYP. .270 TYP. 1 2 3 4 .010 TYP. .430 TYP. .100 .300 .520 MAX. .110 .300 MAX. .050 TYP. DDU8C3-xxA1 (Gull-Wing) Doc #00115 5/19/00 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 DDU8C3 DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: o o Ambient Temperature: 25 C 3 C Supply Voltage (VDD): 3.3V 0.1V Input Pulse: High = 3.3V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.5V and 2.8V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay OUTPUT: Load: Cload: Threshold: 1 CMOS Gate 5pf 10% 1.65V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) T1 T2 T3 T4 T5 IN TRIG TIME INTERVAL COUNTER Test Setup PERIN PWIN TRISE INPUT SIGNAL 2.8V 1.5V 0.5V TFALL VIH 2.8V 1.5V 0.5V VIL TFALL TRISE OUTPUT SIGNAL VOH 1.5V 1.5V VOL Timing Diagram For Testing Doc #00115 5/19/00 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com 4 |
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